Use of minimum-adder multiplier blocks in FIR digital filters

摘要

The computational complexity of VLSI digital filters using fixednpoint binary multiplier coefficients is normally dominated by the numbernof adders used in the implementation of the multipliers. It has beennshown that using multiplier blocks to exploit redundancy across thencoefficients results in significant reductions in complexity overnmethods using canonic signed-digit (CSD) representation, which in turnnare less complex than standard binary representation. Three newnalgorithms for the design of multiplier blocks are described: annefficient modification to an existing algorithm, a new algorithm givingnbetter results, and a hybrid of these two which trades off performancenagainst computation time. Significant savings in filter implementationncost over existing techniques result in all three cases. For a givennwordlength, it was found that a threshold set size exists above whichnthe multiplier block is extremely likely to be optimal. In this region,ndesign computation time is substantially reduced