Modeling, design, and performance analysis of a parallel hybriddata/command driven architecture system and its scalable dynamic loadbalancing circuit

摘要

Addresses a proposed parallel hybrid dataflow architecture, anscalable dynamic load balancing circuit for the proposed architecture,nand performance analysis, first, of the load balancing circuit and,nsecond, the architecture using the load balancing circuit. Thencontributions and focus of this paper are: (1) that it first describesnthe requirements for and the framework of a parallel, medium to coarsengrain, hybrid token controlled dataflow architecture. This paper onlyndeals with real-time applications of the architecture. (2) The papernnext describes the dynamic load balancing strategy for the hybridndataflow architecture and a resulting mathematical model of the loadnbalancing function required by the load balancing strategy. (3) Thenorganization, design, and implementation of a basic digital circuitnsuitable for VLSI implementation which implements the mathematical modelnof the load balancing function required by the architecture is nextnpresented. This circuit implements a control token mapping function andnis therefore called a “token mapper”. (4) It is next shownnthat the basic dynamic load balancing circuit (token mapper) design isnscalable therefore allowing the hybrid dataflow architecture to benscalable. (5) The performance of the dynamic load balancing circuit isnthen analyzed at both the circuit and architectural systems level. Anparallel simulation of the proposed parallel hybrid dataflownarchitecture employing its presented dynamic load balancing circuit wasndeveloped for two example applications and used for architectural systemnlevel performance analysis. Analysis of simulation results verifiedncorrect operation of the proposed hybrid dataflow system architecturenand its dynamic load balancing circuit