Design of ADPLL for both large lock-in range and good trackingperformance

摘要

This paper describes a new all-digital phase locked loop (ADPLL).nThe proposed ADPLL contains a frequency offset estimator and anphase-error estimator. Thereby, it can provide both large lock-in rangenand good tracking performance. Furthermore, it does not suffer severelynfrom the phase jitter due to the quantization effect of the numericallyncontrolled oscillator. In addition to some mathematical performancenanalysis, various simulation and experimental results are also presentednto illuminate further the practical use and the excellent performance ofnthe proposed ADPLL