A new low-power high-speed CMOS buffer, called the charge-transfernfeedback-controlled split-path (CFS) CMOS buffer, is proposed. By usingnthe feedback-controlled split-path method, the short circuit current ofnthe output inverter is eliminated. Four additional MOS transistors arenused as the charge-transfer diodes, which can transfer the charge storednin the split output-stage driver to the output node. Thus thenpropagation delay and power dissipation of the CFS buffer are reduced.nThe HSPICE simulation results show that the power-delay product of thenCFS CMOS buffer is a savings over 20% in comparison to a conventionalnCMOS tapper buffer at 100 MHz operation frequency
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