An on-chip clock-adjusting circuit with sub-100-ps resolution for ahigh-speed DRAM interface

摘要

A novel fully digital fine-delay circuit for a high-speed DRAMninterface is proposed. The circuit consists of arrayed delay componentsnand generates a group of rail-to-rail delayed signals with sub-100-psnresolution. The input-coupling element (squeezer) in the delay componentnconverges the variations of the resolution. A test device design usingn0.35-Μm technology demonstrates that a resolution of 26 ps can benachieved. A clock-recovery circuit using this circuit has antwo-clock-cycle lock time and sub-100-ps error