A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized Gm–C Biquad in 0.13-μ m CMOS

摘要

Fully reconfigurable transceivers are required to answer the low-power high flexibility demand of future mobile applications. This paper presents a fully reconfigurable $G_m$– $C$ biquadratic low-pass filter which offers a large range of both frequency and performance flexibility. First, a design approach is proposed focusing on linearity properties by extending Volterra analysis from circuit to architectural level in order to optimize the filters performance. Secondly, a novel switching technique is discussed that allows a bandwidth tuning over more than two orders of magnitude starting from 100 kHz up to 20 MHz and which uses only gate transistor capacitance. Fundamental to this technique is that the power consumption can be traded with the desired performance. Furthermore, the quality factor, noise level and linearity are all programmable over a very wide range. The biquad is processed in a 0.13- $mu$m CMOS technology and operates at different supply voltages down to less than 0.8 V. For a 1.2-V supply, the filter consumes between 103 $mu$A (100 kHz) and 11.85 mA (20 MHz) for a low noise setting around 25 to 35 $mu$Vrms integrated over the filter bandwidth achieving an third-order intermodulation intercept point of 10 dBVp.