A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique

摘要

A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metal–oxide–semiconductor technology and occupies an active area of 0.068 $hbox{mm}^{2}$ with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step.