A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator

摘要

A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief. This novel comparator architecture is specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments. This brief presents a detailed performance and power analysis of various state-of-the-art comparator designs across three CMOS technologies. At 65-nm technology, with 25% (10%) data activity, the proposed design demonstrates 2.3 $times$ (3.5$times$) and 3.7 $times$ (5.8$times$ ) power and energy–delay product efficiency, respectively. In addition, the proposed work is 2.7 $times$ faster at iso-energy(80 fJ) or 3.3 $times$ more energy efficient at iso-delay(200 ps) than existing designs.