A Delay-Line-Based Voltage-to-Duty-Cycle Controller for High-Frequency PWM Switching Converters

摘要

As the switching frequency of a pulsewidth modulation dc–dc converter increases, the circuit delays become comparable to a switching cycle and raises challenges for the controller design. In this paper, a delay-line-based voltage-to-duty-cycle (V2D) controller is proposed to replace the conventional ramp–comparator-based V2D controller, which significantly simplifies the circuitry and logical complexity of the controller design and relieves the delay-related hassles and limitations for high-frequency converters switching at tens or hundreds of megahertz. The design includes a linearity-compensated voltage-to-current (V2I) cell, a current-starved current-to-duty-cycle (I2D) cell, and a bias current calibration loop, while no ramps or comparators are required. The controller is fabricated in a UMC 0.13- process and measured at 100 MHz, with comparison to a ramp–comparator-based V2D controller. In addition to the benefits of simplified design complexity, the proposed V2D shows an extended controllable duty-cycle range of 0.93 and reduced power consumption by at least half.