A TV Receiver Front-End With Linearized LNA and Current-Summing Harmonic Rejection Mixer

摘要

A low-noise and highly linear wideband receiver front-end composed of the linearized low noise amplifier and current-summing harmonic rejection mixer is implemented in a 0.18- μm CMOS process for TV tuner applications. It shows a measured voltage gain (Av) of more than 34.5 dB, a noise figure of less than 3.5 dB, and a third-order input-referred intercept point (IIP3) of more than −20 dBm in the frequency range from 44 to 880 MHz. The baseband coefficient scaling and summation based on the current mirror ensure a third- and fifth-harmonic rejection ratio of over 45 dBc in measurement with high linearity performance. The power consumption of the proposed TV receiver front-end is 16.2 mW at a 1.8-V supply voltage.