A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design

摘要

This brief presents the design and sizing of a femto-watt voltage reference based on the temperature compensation of N-type and P-type standard transistors. A short-channel dimension transistor working in triode region is added between the source and gate terminals of the traditional self-bias structure, which demonstrates efficient low-power and low-voltage operations. The circuit design was carried out in a 180 nm process. Post-layout simulation results verified the proper circuit operation and produced a reference voltage of 65.7 mV. With a minimum supply voltage of 120 mV, the circuit consumes 252 fW at room temperature, has mean and best temperature coefficients (TCs) of 89.81 ppm/degrees C and 10.61 ppm/degrees C, respectively, from -40 to 120 degrees C, and presents a power supply rejection ratio (PSRR) of -61 dB.