首页> 外文期刊>Circuits and Systems II: Express Briefs, IEEE Transactions on >A 4.5 GΩ-Input Impedance Chopper Amplifier With Embedded DC-Servo and Ripple Reduction Loops for Impedance Boosting to Sub-Hz
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A 4.5 GΩ-Input Impedance Chopper Amplifier With Embedded DC-Servo and Ripple Reduction Loops for Impedance Boosting to Sub-Hz

机译:具有嵌入式DC-SERVO和纹波减速环的4.5GΩ输入阻抗放大器,用于阻抗升压到子Hz

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Achieving a high input impedance Zin is important for the instrumentation amplifier (IA) performing neural and biopotential signal sensing. Previously, impedance boosting techniques have been used with a positive feedback loop (PFL) driven by the output or auxiliary (AUX) path driven by the input. We propose that the conventional approach to DC-servo loop (DSL), which blocks the electrode offset (EOS), does not fully enable the function of a PFL or AUX path. This results in either limited impedance boosting or reduction of a low-frequency Z(in) in the sub-Hz band. To solve this problem and achieve Z(in) boosting down to sub-Hz, we propose a new approach to DSL for a capacitively-coupled chopper instrumentation amplifier (CCIA). The proposed DSL is realized using a 30-nA opamp, and the AUX path is designed using a 450-nA duty-cycled buffer. The CCIA achieves a gain of 40 dB and is implemented using a 0.18 mu m CMOS process with an area of 0.19 mm(2). The measured results show that Zin is increased by 184 times up to 4.6 G Omega at 0.01 Hz. Compared to the CCIA using conventional DSL, Zin is improved by 7.8 times. An input-referred noise of 2.1 mu Vrms is achieved at 2.14 mu W.
机译:实现高输入阻抗Zin对于执行神经和生物电能信号感测的仪表放大器(IA)很重要。以前,已经使用由输入驱动的输出或辅助(AUX)路径驱动的正反馈回路(PFL)使用阻抗升压技术。我们提出了阻止电极偏移(EOS)的DC-伺服环路(DSL)的传统方法不完全启用PFL或AUX路径的功能。这导致子Hz频带中的低频率Z(In)的限制阻抗升高或减小。为了解决这个问题并实现z(in)升压到子hz,我们为电容耦合的斩波器仪表放大器(CCIA)提出了一种新的DSL方法。所提出的DSL使用30-Na Opamp实现,并且使用450-Na循环缓冲液设计Aux路径。 CCIA实现了40dB的增益,并使用0.18 mu M CMOS工艺实施,面积为0.19mm(2)。测量结果表明,锌在0.01Hz时增加了184倍,高达4.6gω。与使用常规DSL的CCIA相比,Zin提高了7.8倍。 2.1μmVrms的输入引用噪声在2.14 mu w.

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