A 0.65-V, 11.2-Gb/s Power Noise Tolerant Source-Synchronous Injection-Locked Receiver With Direct DTLB DFE

摘要

This brief presents a 0.65-V power noise tolerant source-synchronous injection-locked receiver with 13.4 dB channel loss compensation. To meet the 1UI timing constraint for the decision feedback equalizer in low supply, SR latches are removed in the feedback path and return to zero recovered data is used for equalization. Additionally, a power noise sensitivity of low supply is relieved by current and pMOS body bias control techniques of an oscillator. The test core fabricated in 65-nm CMOS process achieves 11.2 Gb/s with 0.303 pJ/bit FOM compensating 13.4 dB channel loss at 5.6 GHz.