A Histogram-Based Background Interstage Error Estimation and Implementation Method in Pipelined ADCs

摘要

This brief presents a new method to estimate the interstage gain error and sub-DAC nonlinearity in pipelined ADCs, regardless of the number of bits per stage. The method is based on the effect of error on the ADC output histogram and estimates errors in the background. It means that no special input signal is required and no interruption occurs during the estimation process. The method imposes no limitation on input bandwidth nor on its distribution. The proposed method is robust against noise and memory error of comparators. The estimation process is very fast and its implementation is simple compared to other techniques.