Debugging VHDL designs using model-based reasoning

摘要

The application of formal methods in software engineering and hardware design has become an important field of research. It aims at minimizing time to market and reduce the overall development costs. While formal verification, e.g. model-checking, is widely used, methods for helping programmers or engineers in locating and fixing faults within a hardware design or software are rarely available. In this paper we describe part of the advanced diagnosis and measurement selection capabilities of the model-based diagnosis tool VHDLDIAG designed for (semi)automatically locating bugs in VHDL programs. VHDL is an Ada-like and widely used hardware description language. VHDL programs are converted into logical descriptions which are then used by a diagnosis engine for detecting the parts of the program responsible for an observed misbehavior. The results of diagnosis, i.e. the malfunctioning program fragments, are mapped back to the program code. Because of the logical description used VHDLDIAG can be applied to a wide range of programs from small to very large ones with up to thousands of MBytes of source code. This paper presents techniques which use multiple versions of a design in diagnosis, as well as the measurement selection process used in VHDLDIAG. Formal definitions and performance results using real-world VHDL programs are given.