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首页> 外文期刊>Applied Surface Science >Fabrication of 0.12 μm pMOSFETs on high Ge fraction Si/Si_(1-x)Ge_x/Si(100) heterostructure with ultrashallow source/drain formed using B-doped SiGe CVD
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Fabrication of 0.12 μm pMOSFETs on high Ge fraction Si/Si_(1-x)Ge_x/Si(100) heterostructure with ultrashallow source/drain formed using B-doped SiGe CVD

机译:在高Ge分数Si / Si_(1-x)Ge_x / Si(100)异质结构上使用B掺杂SiGe CVD形成具有超浅源极/漏极的0.12μmpMOSFET的制造

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摘要

High Ge fraction Si/Si_(1-x)Ge_x/Si heterostructures (x = 0.5) are processed into the super self-aligned ultrashallow junction electrode (S~3E) pMOSFETs. The ultrashallow junction is made from the selective epitaxial B-doped Si_(0.5)Ge_(0.5) on source/drain grown by chemical vapor deposition (CVD) and subsequent thermal diffusion of B from B-Si_(0.5)Ge_(0.5) into the substrate. The Ge fraction in the S~3EMOSFETs' buried layer changes to 0.35 after the B diffusion at 750℃ due to the interdiffusion between Si and Ge. The B diffusion depth in Si/SiGe/Si is shallower compared to that in Si. Compared to Si-channel S3EMOSFET, the maximum linear transconductance of the 0.12 μm gate Si_(0.65)Ge_(0.35)-channel S~3EMOSFET increases by approximately 45%. The threshold voltage shift and the S factor degradation in the short channel region are well suppressed compared to the Si-channel S~3EMOSFETs. It is suggested that the suppression of short channel effects is caused by the ultrashallow source/drain and the valence band discontinuity at the Si_(1-x)Ge_x/buffer Si interface.
机译:将高Ge分数的Si / Si_(1-x)Ge_x / Si异质结构(x = 0.5)处理到超自对准超浅结电极(S〜3E)pMOSFET中。超浅结由通过化学气相沉积(CVD)生长的源/漏上的选择性外延掺B的Si_(0.5)Ge_(0.5)以及随后B从B-Si_(0.5)Ge_(0.5)的热扩散到基板。由于Si和Ge之间的相互扩散,在750℃下B扩散之后,S〜3EMOSFET的埋层中的Ge分数变为0.35。与Si相比,Si / SiGe / Si中的B扩散深度更浅。与Si沟道S3EMOSFET相比,0.12μm栅极Si_(0.65)Ge_(0.35)沟道S〜3EMOSFET的最大线性跨导增加了大约45%。与Si沟道S〜3EMOSFET相比,在短沟道区域中的阈值电压漂移和S因子劣化得到了很好的抑制。建议短沟道效应的抑制是由Si_(1-x)Ge_x / buffer Si界面的超浅源极/漏极和价带不连续引起的。

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