Characteristics of Superconducting First-Order Sigma-Delta Modulator With Clock-Doubler Circuit

摘要

Superconducting first-order sigma-delta modulator was designed and evaluated experimentally at the sampling frequency $({rm f}_{rm s})$ over 10 GHz using an internal clock-doubler circuit. We employed a complementary-feedback type first-order sigma-delta modulator with an LR integrator. The numerical simulation indicated that higher ${rm f}_{rm s}$ of 20 GHz are required to achieve 14-bit resolution for the signal bandwidth of 10 MHz. We newly developed a frequency doubler circuit to generate 20 GHz clock signals from external 10 GHz signals. The modulator could be evaluated experimentally at ${rm f}_{rm s}$ up to 16 GHz, which limited by the measurement system. The measured SINAD (signal-to-noise-and-distortion ratio) of the modulator is almost equal to the numerically simulated value, and the SINAD at 16 GHz is about 77 dB for the signal bandwidth of 10 MHz.