A New Design Methodology for Single-Flux-Quantum (SFQ) Logic Circuits Using Passive-Transmission-Line (PTL) Wiring

摘要

The introduction of passive-transmission-line (PTL) wiring to large-scale SFQ logic circuits offers several advantages over traditional Josephson-transmission-line (JTL) wiring, such as smaller wiring area, less delay, lower power consumption, and more freedom in routing. PTL wiring can drastically change the style of designing SFQ logic circuits. We propose a new methodology for designing large-scale SFQ circuits using PTL wiring. Aiming at generalizing SFQ circuit design, we chose synchronous clocking. We developed a placer that was suitable for SFQ circuit design to assist us with the new design methodology. The placer first synthesizes an H-tree clock distribution network, placing SFQ pulse splitter cells at each branch. It then places logic cells to minimize the maximum length of data PTL wires, aiming at higher operating speeds. Finally, a router completes the PTL wiring. To evaluate the design methodology we designed an 8-bit general purpose RISC processor. Within twelve hours, we obtained a 15-mm-square SFQ circuit that could operate up to 27.6 GHz. We adopted an advanced Nb process, which was characterized by a critical current density of 10 ${rm kA}/{rm cm}^{2}$, two 5-$mu{rm m}$-wide PTL wiring layers, and a minimum cell size of $30 mu{rm m}times30 mu{rm m}$. The circuit consisted of about 20,000 logic cells, which approximated more than 400,000 Josephson junctions including splitters to distribute the clock signal.