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Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement

机译:基于电荷等离子体技术的无掺杂累积模式无结圆柱形环绕栅MOSFET:模拟性能改进

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摘要

A charge plasma technique based dopingless (DL) accumulation mode (AM) junctionless (JL) cylindrical surrounding gate (CSG) MOSFET has been proposed and extensively investigated. Proposed device has no physical junction at source to channel and channel to drain interface. The complete silicon pillar has been considered as undoped. The high free electron density or induced N+ region is designed by keeping the work function of source/ drain metal contacts lower than the work function of undoped silicon. Thus, its fabrication complexity is drastically reduced by curbing the requirement of high temperature doping techniques. The electrical/analog characteristics for the proposed device has been extensively investigated using the numerical simulation and are compared with conventional junctionless cylindrical surrounding gate (JL-CSG) MOSFET with identical dimensions. For the numerical simulation purpose ATLAS-3D device simulator is used. The results show that the proposed device is more short channel immune to conventional JL-CSG MOSFET and suitable for faster switching applications due to higher I_(ON)/I_(OFF) ratio.
机译:已经提出并广泛研究了基于电荷等离子体技术的无掺杂(DL)累积模式(AM)无结(JL)圆柱环绕栅(CSG)MOSFET。拟议的器件在源到通道和通道到漏极的接口上没有物理结。完整的硅柱被认为是未掺杂的。高自由电子密度或感应N +区的设计是通过使源极/漏极金属触点的功函数低于未掺杂硅的功函数来进行的。因此,通过抑制高温掺杂技术的要求,大大降低了其制造复杂性。已使用数值模拟对拟议器件的电/模拟特性进行了广泛研究,并将其与尺寸相同的常规无结圆柱形环绕栅(JL-CSG)MOSFET进行了比较。为了进行数值模拟,使用了ATLAS-3D设备模拟器。结果表明,由于较高的I_(ON)/ I_(OFF)比,该器件对常规JL-CSG MOSFET具有更短的免疫力,并适合于更快的开关应用。

著录项

  • 来源
    《Applied Physics 》 |2017年第9期| 564.1-564.7| 共7页
  • 作者单位

    Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110021, India;

    Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110021, India;

    Department of Physics, Motilal Nehru College, University of Delhi, New Delhi 110021, India;

    Department of Electrical and Electronics Engineering, Maharaja Agrasen Institute of Technology, New Delhi 110086, India;

    Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi South Campus, New Delhi 110021, India;

    Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi 110086, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
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  • 正文语种 eng
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