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High-quality HfSi_xO_y gate dielectrics fabricated by solid phase interface reaction between physical-vapor-deposited metal-Hf and SiO_2 underlayer

机译:通过物理气相沉积金属Hf和SiO_2底层之间的固相界面反应制备的高质量HfSi_xO_y栅极电介质

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摘要

We fabricated high-quality Hf-silicate (HfSi_xO_y) gate dielectrics by utilizing the solid phase interface reaction between physical-vapor-deposited metal-Hf (typically 0.5 nm thick) and SiO_2 underlayers. Metal diffusion to the SiO_2 layer increases the permittivity of the underlayer, while preservation of the initial SiO_2/Si bottom interface ensures good electrical properties of the gate dielectrics. The Hf-silicate layer remains amorphous and the poly-Si/HfSi_xO_y gate stack endures activation annealing at 1000℃. The interface trap density was comparable to that of conventional SiO_2 dielectrics and the hysteresis of capacitance-voltage curves was as low as 4 mV for a bias swing between -2 and +2.5 V. Moreover, high electron mobility, equal to 89% of the universal mobility, was obtained for the high-k gate transistor.
机译:通过利用物理气相沉积的金属Hf(通常为0.5 nm厚)与SiO_2底层之间的固相界面反应,我们制造了高质量的Hf硅酸盐(HfSi_xO_y)栅极电介质。金属向SiO_2层的扩散增加了底层的介电常数,同时保留了最初的SiO_2 / Si底部界面可确保栅极电介质的良好电性能。 Hf-硅酸盐层保持非晶态,并且多晶硅/ HfSi_xO_y栅堆叠在1000℃下经受激活退火。界面陷阱密度可与常规SiO_2电介质媲美,并且在-2至+2.5 V的偏压摆幅下,电容-电压曲线的滞后性低至4 mV。此外,高电子迁移率相当于电子迁移率的89%。高k栅极晶体管获得了通用迁移率。

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