Random telegraph signal in nanoscale back-side charge trapping memories

摘要

Random telegraph signal (RTS) was observed in the front and back channel source-drain current of nanoscale double-gated back-side charge trapping memories. The front gate dielectric is silicon oxide and the back gate dielectric is a stack of silicon oxide-silicon nitride-silicon oxide (ONO). The structure provides a tool for traps characterization at multiple interfaces and combinations of materials. Bias dependence of RTS due to a trap in the back ONO was measured to determine the position of the trap in the dielectric. The results show that the individual trap is located within the tunneling oxide, 1.3 nm away from the silicon interface. RTS due to traps responsible for the memory properties, located in the silicon nitride or its interface, was not observed.