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Optimized design of a digital I/Q demodulator suitable for adaptive pre-distortion of 3rd generation base station PAs

机译:适用于第三代基站PA自适应预失真的数字I / Q解调器的优化设计

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This article presents an optimized design of a high-speed digital I/Q demodulator intended for the implementation of the feedback path of an adaptive base band digital pre-distorter (DPD). Indeed, the optimization of the DPD linearization capability, in terms of correction bandwidth and nonlinearity effects minimization, is directly related to the accuracy and speed of the I/Q demodulator. In this work, a digital I/Q demodulator is designed, optimized and implemented in a Xilinx FPGA device. This allowed for high-speed processing of about 200 MHz with a substantial reduction in the FPGA used gates.
机译:本文提出了一种高速数字I / Q解调器的优化设计,旨在实现自适应基带数字预失真器(DPD)的反馈路径。实际上,就校正带宽和非线性效应最小化而言,DPD线性化能力的优化与I / Q解调器的精度和速度直接相关。在这项工作中,在Xilinx FPGA器件中设计,优化和实现了数字I / Q解调器。这允许大约200 MHz的高速处理,同时大大减少了FPGA使用的门。

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