Low-power interface circuits between adiabatic and standard CMOS circuits

摘要

The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. All interface circuits and their layouts are implemented using TSMC 0.18 μm CMOS technology. The function verifications and energy loss tests for all interfaces are carried out using the net-list extracted from the layout. Full parasitic extraction is done. An adiabatic 8-bit carry look-ahead adder embedded in a static CMOS circuits is used to verify the proposed interfaces. The proposed interface circuits attain large energy savings over a wide range of frequencies, as compared with the previously reported circuits.