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A low power direct conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise

机译:具有高带内IIP2 / IIP3和低1 / f噪声的低功率直接转换接收器RF前端

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A low power direct-conversion receiver RF front-end with high in-band IIP2/IIP3 and low 1/f noise is presented. The front-end includes the differential low noise amplifier, the down-conversion mixer, the LO buffer, the IF buffer and the bandgap reference. A modified common source topology is used as the input stages of the down-conversion mixer (and the LNA) to improve IIP2 of the receiver RF front-end while maintaining high IIP3. A shunt LC network is inserted into the common-source node of the switching pairs in the down-conversion mixer to absorb the parasitic capacitance and thus improve IIP2 and lower down the 1/f noise of the down-conversion mixer. The direct-conversion receiver RF front-end has been implemented in 0.18 µm CMOS process. The measured results show that the 2 GHz receiver RF front-end achieves +33 dBm in-band IIP2, 21 dB power gain, 6.2 dB NF and −2.3 dBm in-band IIP3 while only drawing 6.7 mA current from a 1.8 V power supply.
机译:提出了一种具有高带内IIP2 / IIP3和低1 / f噪声的低功率直接转换接收器RF前端。前端包括差分低噪声放大器,下变频混频器,LO缓冲器,IF缓冲器和带隙基准。修改后的公共源拓扑用作下变频混频器(和LNA)的输入级,以改善接收机RF前端的IIP2,同时保持较高的IIP3。在下变频混频器的开关对的共源节点中插入并联LC网络,以吸收寄生电容,从而改善IIP2并降低下变频混频器的1 / f噪声。直接转换接收器RF前端已采用0.18 µm CMOS工艺实现。测量结果表明,2 GHz接收器射频前端可实现+33 dBm带内IIP2、21 dB功率增益,6.2 dB NF和-2.3 dBm带内IIP3,而仅从1.8 V电源汲取6.7 mA电流。

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