To obtain a high performance CMOS resistor string digital-to-analog converter (DAC), one of the key design issues is the mismatch in the resistor ratio. This mismatch causes nonlinearity errors such as integral nonlinearity (INL) and differential nonlinearity (DNL), degrading the performances of the converter. Usually these matching properties are taken into account during the design phase by using time consuming and computational intensive transistor-level Monte Carlo simulations for the process technology corner. Recent research aims at reducing the design time by exploiting high-level modeling of converters as a trade-off between simulation time and modelling accuracy. In this work an analytical model for resistor mismatch in DACs is presented and implemented in MATLABTM environment. The model utilizes geometrical size of resistors and statistical data of the technology process. Starting from random process variations on geometries it was possible to estimate DNL and INL with very short time simulations. The proposed model is valid both for single stage resistor string DACs or segmented ones. The model can be used to speed up the design of resistor-string based DACs, or as a starting point to develop more accurate models by taking into account high-order effects. The model was successfully used to design a 10bit resistor string DAC in a 0.18 μm BCD technology with DNL and INL lower than 1 LSB (in absolute value). Since the complexity of the DAC is dominated by the resistor string, its optimization since the early design steps, enabled by the proposed high-level model, allowed to minimize area versus state of the art.
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