Novel system clock generation from a modulated signal

摘要

This paper describes a novel technique to derive a pure-spectral system clock with a common multi-modulus divider from a frequency modulated signal. Therefore, the dividing factor is inverse frequency modulated to compensate the frequency modulation component on the divider input signal. Additionally, $UpsigmaUpdelta$ dithering is applied to the frequency divider. The technique is used for a FM-radio transmitter based on an all-digital phase-locked loop (PLL) to generate a higher-frequency clock for baseband signal processing. It can also be applied to other PLL based transmitters or receivers, especially, if only a slow PLL reference clock is available and a faster system or baseband clock is required. The main factor determining the quality of the generated clock signal is the PLL’s reference quartz oscillator as it determines the accuracy of the PLL’s RF oscillator, which limits then the accuracy of the newly generated clock. In the FM-radio transmitter, a generated ≈1 MHz clock signal with 30.58 ppm frequency offset and 515 ps root mean square jitter is generated. The phase noise is determined to −83.5 dBc/Hz at 10 kHz offset and −70.5 dBc/Hz at 1 kHz, respectively. The signal can also be used in co-integrated or external circuits.