A 8 mW 72 dB ΣΔ-modulator ADC with 2.4 MHz BW in 130 nm CMOS

摘要

A double-sampling split ΣΔ-ADC with bilinear integrators and a 7-level quantizer is presented. It achieves third order noise shaping with a second order modulator through quantization noise-coupling. The modulator is integrated in a 130 nm CMOS technology. For a clock frequency of 48 MHz and an oversampling ratio of 20 (2.4 MHz signal bandwidth), it achieves 72 dB DR and 68 dB SNR. The prototype consumes 8 mW from a 1.2 V voltage supply.