An effective deterministic test generation for test-per-clock testing

摘要

Effective testing to ensure the reliability of integrated circuit (IC) is particularly important, especially in military, aerospace, communications, and other felds. A traditional circuit test structure is shown in Figure 1. Test stimuli are applied to the circuit under test (CUT), and test responses are analyzed so as to determine any fault exists. Traditional testing is faced with several serious challenges. First, larger scale IC testing leads to a higher requirement of storage capacity. Second, more test channels and long test application time (TAT) are needed. Third, some kinds of interconnect faults, such as delay faults, may only occur at high frequency of signal changes [1]. In order to guarantee high quality of testing, at-speed testing becomes imperative. All of these lead to an unaccept-ably increasing cost for automatic testing equipment (ATE).