一种RS(15,9)译码器的FPGA实现

摘要

A solution of RS(15,9) decoder based on a new intra-region multiplicator using an FPGA device is presented. The decoder acquires the ability of real-time processing by designing rational, pipeline, modularized structure. Based on the characteristic of intra-region multiplication, the logical AND-XOR calculus form is deriued according to equiualent bit. FPGA has plentiful logical resource, which makes intra-region multiplicator working in the higher frequency section. The intra-region division is divided into multiplication and inverse operation, and the inverse operation adopt the table look-up method, making full use of the SLICE register resource inside the FPGA. The simulation shows this decoder is real-time and suitable for the occasion that requires processing speed rigorously.%提出一种基于新的域内乘法器的RS(15,9)译码器FPGA解决方案,通过设计合理的流水线和模块化结构,使得此译码器具有实时处理的能力.根据域内乘法的特点,导出域内乘法器的等效按比特与异或逻辑运算形式.FPGA内部有大量的逻辑资源,利用这些逻辑实现的域内乘法器可以工作在更高的频率.将域内除法分解为乘法和求逆两部分,其中求逆运算采用查表法,充分利用FPGA内部SLICE的寄存器资源.仿真表明此译码器可以应用于对处理速度要求苛刻的场合,并且具有实时译码的能力.