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A Modified Algorithm for QRS Complex Detection for FPGA Implementation

机译:一种用于FPGA实现的QRS复杂检测的改进算法

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This work is part of the Psypocket project which aims to conceive an embedded system able to recognize the stress state of an individual based on physiological and behavioural modifications. In this paper, one of the physiological data, the electrocardiographic (ECG) signal, is focused on. The QRS complex is the most significant segment in this signal. By detecting its position, the heart rate can be learnt. In this paper, a field-programmable gate array (FPGA) architecture for QRS complex detection is proposed. The detection algorithm adopts the integer Haar transform for ECG signal filtering and a maximum finding strategy to detect the location of R peak of the QRS complex. The ECG data are originally recorded by double-precision decimal with the sampling frequencies of 2000 Hz. For the FPGA implementation, they should be converted to integers with rounding operation. To find the best multiplying factor for rounding, the comparison is performed in MATLAB. Besides, to reduce the computation load in FPGA, the feasibility of the reduction in the sampling frequency is tested in MATLAB. The FPGA Cyclone EP3C5F256C6 is used as the target chip, and all the components of the system are implemented in VHSIC hardware description language. The testing results show that the proposed FPGA architecture achieves a high detection accuracy (98.41%) and a good design efficiency in terms of silicon consumption and operation speed. The proposed architecture will be adopted as a core unit to make a FPGA system for stress recognition.
机译:这项工作是Psypocket项目的一部分,该项目旨在构思一个嵌入式系统,该系统能够根据生理和行为改变来识别个人的压力状态。在本文中,重点研究了一种生理数据,即心电图(ECG)信号。 QRS复合信号是此信号中最重要的部分。通过检测其位置,可以了解心率。本文提出了一种用于QRS复杂检测的现场可编程门阵列(FPGA)架构。该检测算法采用整数Haar变换进行ECG信号滤波,并采用最大发现策略来检测QRS波群R峰的位置。心电图数据最初以双精度十进制形式记录,采样频率为2000 Hz。对于FPGA实现,应使用舍入运算将其转换为整数。为了找到最佳的四舍五入乘数,在MATLAB中进行比较。另外,为了减轻FPGA的运算量,在MATLAB中测试了降低采样频率的可行性。 FPGA Cyclone EP3C5F256C6用作目标芯片,系统的所有组件均以VHSIC硬件描述语言实现。测试结果表明,所提出的FPGA架构在硅消耗和运算速度方面具有很高的检测精度(98.41%)和良好的设计效率。拟议的架构将被用作制造用于应力识别的FPGA系统的核心单元。

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