An algorithm has been developed for the simultaneous measurement of the fetal and maternal heart rates from the maternal abdominal electrocardiogram during pregnancy and labor for fetal monitoring. The algorithm is based on crosscorrelation, adaptive thresholding and statistical properties in the time domain. Hardware description language - VHDL has been used to implement the algorithm for FPGA implementation. The design is synthesized and fitted into Altera's Stratix EP1S10 using the Quartus II platform. Test case results showed an error percentage of around ᰮ3% and ᰮ5% for the detection of maternal and fetal heart rate respectively.
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