Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C

摘要

Reed Solomon coding has an important role to play as to sustain reliability of data communication. However, the encoder consumes significant amount of power that affects the cost of producing the hardware. Besides, the complicated encoder circuit also does affect the cost of implemented hardware. There is a need to build a simple encoder which does the similar data encoding function. By amalgamate One Instruction Set Computer (OISC) and the Galois Field arithmetic, a Reed Solomon Minimal Instruction Computer (MISC) processor is developed. This processor has simpler circuit that still has the same encoded codeword produced.