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基于乒乓操作的千兆MAC中的FIFO设计

         

摘要

针对机栽一体化高帧频相机设计中存在的高速图像数据的传输问题,提出一种在FPGA芯片上开发千兆MAC的实时解决方案.采用千兆MAC和外部PHY相结合的方式设计千兆网卡,实现高速实时传输高帧频视频图像数据的目的.设计中采用FPGA内嵌的块存储,在千兆MAC核内设计同步FIFO,利用Verilog硬件描述语言,在XILINX FPGA的编辑环境ISE中进行了综合,在Modelsim中做了仿真,结果表明:读写时钟为250MHz时,能够对FIFO正确读写,产生正确的标志信号,实现数据缓存的功能.仿真和实际测试结果验证了方案的可行性.%A real-time design of a gigabit MAC based on a FPGA chip is proposed to resolve the high-speed image data transmission problems existing in the airborne integration design of a high-frame-rate camera. A gigabit network card composed of an ethernet media access control (MAC) and an external PHY is designed to realize the real-time high-speed transmission of video and image data of the high-frame-rate camera. A synchronous FIFO in the gigabit MAC core is designed using a FPGA-chip-embedded block RAM. The FIFO is designed using the Verilog HDL, synthesized in the ISE design environment of XILINX FPGA and simulated in Modelsim. The results show that the FIFO can be written and read with correct produced flag signals at a writing and reading clock of 250MHz and that the FIFO can realize the function of data cache. The feasibility of the proposal is verified in both simulation and real test.

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