CPLD器件的出现给现代电子设计带来了极大的方便和灵活性,使复杂的数字电子系统设计变为芯片级设计,同时还可以很方便地对设计进行在线修改.首先介绍了频率计的测频原理,然后利用CPLD芯片进行测频计数,从而实现了简易数字频率计的设计.此频率计的设计采用基于VHDL的“Top-Down”(自上而下)的设计方法,从系统总体要求出发,自上而下地逐步将设计内容细化,最后完成系统硬件的整体设计.所设计的电路在GW48系列SoPC/EDA实验箱上通过硬件仿真,下栽到目标器件上运行,能够满足实际测量频率的要求.%The component of CPLD provided enormous convenience and flexibility for the modern electronic design, which changed the complicated digital electronic system design into chip design and performed the online modification for the design conveniently. The frequency measurement principle of the frequency meter is introduced, the method of using CPLD to count the frequency of the signal for completing the design of the simple digital frequency meter is proposed. The frequency meter used the VHDL-based "Top-Down" design method, set out the total requirement of system, refined the design content by "Top-Down" method and achieved the design of hardware finally. The designed circuit was simulated, programmed on the aim device and ran on series SoPC /EDA experiment chest. The design can meet the requirement of the practical frequency measurement.
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