SoC中跨时钟域的信号同步设计

摘要

In SoC design, the handling of multiclock domain is an important step. The catastrophic effect will occur in the design if the designers do not pay enough attention to the special problems. When the data is transmitted across the clock domains, how to successfully complete data transmission and maintain system stability is a focus to each designer. The metasta-bility and the impact caused by the asynchronous signal in the multiclock domain on the functions of the entire circuit are discussed in this paper. For asynchronous transmission of the single signal, four basic synchronous units (the synchronization of pulse to pulse, the synchronization of pulse to level, the synchronization of level to level, the synchronization of level to pulse) are put forward on the basis of the synchronizer composed of dual trigger. The emphasis is that these four synchronous elements have no requirement to asynchronous clock frequency. The circuit diagrams of the four synchronizers are given.%多时钟域的处理是系统级芯片(SoC)设计中的一个重要环节.如果对其中出现的特殊问题估计不足,将对设计造成灾难性后果.数据跨时钟域传输时如何保持系统的稳定,顺利完成数据的传输是每个设计者都需要关注的问题.在此讨论了在多时钟域中异步信号带来的亚稳态及对整个电路性能和功能的影.针对单一信号的异步传榆,在已有的双触发器构成的同步器的基础上提出了4种同步单元:脉冲到脉冲的同步、脉冲到电平的同步、电平到电平的同步,电平到脉冲的同步.值得强调的是这4种同步器都对异步时钟频率没有大小关系的限制.并且给出了4种同步器的电路结构图并进行了实现,使得数据传输更加稳定可靠.