To solve the problems of complex circuit, difficult design and poor performance existing in previous, systems, a new design method of all digital phase-locked loop (ADPLL) is proposed in this paper. The new ADPLL is realized by propor-tional-integral (PI) method rather than by conventional digital loop filtering control methods. The whole system is designed by using EDA technology and simulated by using computer. Simulation results shows, in certain frequency range, the longest time for the loop arriving its locked state is less then 15 cycles of the input signal, and the phase jitters is less than 5% of the output signal cycle. In addition, it has characteristics of simple structure, excellent loop performance, easy integration, etc.%针对以往全数字锁相环研究中所存在电路结构复杂、设计难度较大和系统性能欠佳等问题,提出了一种实现全数字锁相环的新方法.该锁相环以数字比例积分控制的设计结构取代了传统的一些数字环路滤波控制方法.应用EDA技术完成系统设计,并进行计算机仿真.仿真结果表明:在一定的频率范围内,该锁相环锁定时问最长小于15个输入信号周期,相位抖动小于输出信号周期的5％,且具有电路结构简单、环路性能好和易于集成的特点.
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