Field Programmable Gate Arrays-Nanotechnology Based Analysis, Design and Implementation of All-Digital Phase Locked Loop

摘要

The paper presents a new technique to improve the performance of All-Digital Phase Locked Loop (ADPLL) IP core on FPGA Nanotechnology. The FPGA maintains the advantages of custom functionality like an ASIC while avoiding the high development costs and the inability to make design modifications after production. If excellent platforms like FPGA have the support of predefined and pre-verified IP cores, the concept of 24 hour system on chip is very much possible. The current design of ADPLL IP core is meant for this very purpose. Implementation of a digital PLL on a FPGA helps to control the jitter involved in the operation of PLLs to a greater extent that is troubling the current communication industry. The proposed work in this paper compare favorably with previously proposed approaches. The focus of this work is on design, analysis and implementation of ADPLL on Xilinx FPGA-Nanotechnology platform.