针对传统锁相环研究中电路结构复杂、鉴相精度不高、锁相范围窄等问题，提出一种新型全数字锁相环。与传统锁相环相比，鉴相模块中的时间数字转换电路能将鉴相误差转换为高精度数字信号，一种双边沿触发的数字环路滤波器取代了传统的数字环路滤波器的电路结构，采用可变模分频器来替换传统的固定模分频器。应用EDA技术完成了系统设计，并采用 QuartusⅡ软件进行了系统仿真验证。仿真结果表明：该锁相环锁相范围约为800 Hz~1 MHz，系统锁定时间最快为10个左右输入信号周期，且具有锁相范围大、精度高、电路结构简单和易于集成等特点。%In view of complex circuit structure,inaccurate phase detection precision and narrow phase⁃locked range of the traditional phase⁃locked loops(PLL),a new type of all⁃digital phase⁃locked loop is proposed in this paper. Compared with the conventional ones,the time⁃to⁃digital conversion circuit in the phase detection module can transform the phase detection error to high⁃precision digital signal. Therefore,the traditional digital filter with loop structure is replaced by the double⁃edge triggered digital loop filter,and a variable modulus frequency divider is adopted to take the place of the classic fixed mode frequency di⁃vider. The system design is fulfilled by means of EDA technology while its simulation verification is implemented with QuartusⅡsoftware. The simulation results show that the locking range of the phase⁃locked loop is within the frequency from 800 HZ to 1 MHZ,and the lock⁃in time is about 10 times of the input signal cycles. In addition,it has the characteristics of broad phase⁃locked range,high accuracy,simple circuit structure and easy integration.
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