基于嵌入式微处理器IP核的SoC物理设计

摘要

The method and flow of physical design for IP hard core and SoC based on embedded Micro Processor Unit (MPU) IP core are introduced in this paper. Several methods are explored to solve the contradiction between the complicated system structure and the limited physical implementation area of SoC based on MPU IP core, such as changing memory type of Cache, reducing the pins of IP core, placing pins on double sides of IP core, distinguishing high frequency clock signal from low frequency clock signal, optimizing the power network and using four-line Pad bonding for the top design of SoC, so the physical implementation area can be reduced, and the timing slack can be optimized. The test results of the fabricated SoC show that the highest work frequency of the embedded MPU in the designed SoC can reach 500MHz at the condition of normal temperature (25℃) and normal power supply (1.2V), the function is correct, and the power consumption is smaller than 2.0mW/MHz. This paper has reference value for customization of IP hard core, design of SoC and VLSI design using standard cell library and reusable IP cores.%介绍了嵌入式微处理器IP硬核及SoC的物理设计方法和流程.针对SoC的复杂系统结构与有限物理实现面积之间的矛盾,通过采用改变Cache存储器类型、减少IP核引脚数量、IP核双边摆放引脚、区分高低频时钟、优化电源网络以及SoC顶层采用四层引出Pad等措施,对减小物理实现面积,优化时序特性的方法进行了一些探索.SoC电路经测试,其结果表明,SoC电路内嵌的微处理器在常温(25℃)常压(1.2V)条件下最高工作频率可以达到500MHz,功能正确,功耗小于2.0mW/MHz.这些措施对IP硬核的实现、SoC设计及基于标准单元库和可复用IP核的超大规模集成电路设计,具有一定的指导意义.