Continuing trends in computer systems have adversely effected the ability of VLSI chip designers to operate graphically on any significant fraction of a layout in an interactive or accurate manner using current methods. While transistor counts of designs have grown at the rate given by Moore's Law, key components contributing to the real-time and accurate display with existing methods (CPU to memory bandwidth, CPU to GPU bandwidth, monitor resolution) have not grown as fast. Consequently, when using today's CAD systems to view a large chip at low zoom, the display can take dozens of seconds or more to refresh and the resulting image can contain visually misleading artifacts which yield no clues about the design's structure.; We present a new visualization infrastructure for VLSI physical design datasets called a “chipmap.” First, we show how it can be used to visualize the canonical VLSI database, the layout, in an accurate, interactive, and fluid manner. Visual fidelity is achieved with standard computer graphics anti-aliasing techniques modified to take advantage of the special rectilinear, hierarchical, and layer dependence properties inherent to VLSI datasets. Interactivity is realized by using texture mapping and mipmapping so the information sent to the display is bounded, and the image rendered on the display is filtered correctly.; Our experimental implementation shows that real-time navigation can be achieved on arbitrarily large layouts with a reasonable memory overhead. Results also show an average image error of about 2% (RMS error) between our images and rigorously generated “perfect” images while other layout systems produce errors up to 38% when compared to these images.; Next, we extend the use of a chipmap showing how it can be used to visualize other types of VLSI physical design data. Common operations include selecting feature sets, back-annotating analysis information and computing device densities. Using these tools, we demonstrate additional accurate and interactive visualizations of floorplan, DRC, critical timing paths, clock skew, and other information.
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