首页> 中文期刊> 《西安邮电学院学报》 >非规则串行程序隐式线程级推测并行发展综述

非规则串行程序隐式线程级推测并行发展综述

         

摘要

Based on the system structure of chip multiprocessor (CMP),the development and research status,characteristics and challenges of implicit TLS parallel technology in the field of automatic parallelization of the traditional irregular serial program are reviewed in this paper.A thorough and detailed analysis are conducted on four aspects of the TLS technique,namely program feature analysis,multi-thread partitioning,accelerating method based on hardware and software co-design,and performance and power consumption evaluation.Directions of TLS technology in the future development and some possible research ideas are also presented.%基于片上多核处理器体系结构,概述在非规则串行程序自动并行化领域中,隐式线程级推测并行技术的特点、研究现状、以及所面临的挑战.从程序特征分析、多线程划分、软硬件协同加速方法和性能功耗评估等4个方面,探讨线程级推测技术未来的发展趋势和研究方向.

著录项

相似文献

  • 中文文献
  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号