为了有效降低容忍软错误设计的硬件和时序开销，该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略，综合运用触发器替换和复制门法。第1阶段，基于时序优先的原则，在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路；第2阶段，在时序紧张的路径使用复制门法进行加固。和传统方案相比，该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU)，又减少了面积开销。ISCAS’89电路在45 nm工艺下的实验表明，平均面积开销为36.84%，电路平均软错误率降低99%以上。%In order to reduce effectively the hardware and timing overhead for circuit soft-error-tolerance, a hybrid hardening technique for soft error tolerance is proposed based on timing priority in this paper. A two-stage hardening strategy is exploitsed by using flip-flop replacement and duplicated gate method to harden circuit. At first stage, based on the timing priority principle, high reliability temporal redundancy flip-flop is used to harden circuit on the path of timing slack. At second stage, duplicated gate method is used on timing sensitive path. Compared with traditional techniques, the proposed technique can not only mask the Single Event Transient (SET) and protect against the Single Event Upset (SEU), but also reduce the overhead of the area. The experiment result of ISCAS’89 benchmark circuits in 45 nm Nangate process proves that the circuit average soft error rate is reduced by more than 99%and the average area overhead is 36.84%.
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