The Godson-2G microprocessor is a high performance SOC which integrates a four-issue 64-bit high performance CPU core(called GS464),a DDR2/3 controller,a HyperTransport controller,a PCI/PCI-X controller,etc.It is physically implemented in 65 nm CMOS process and reaches the frequency of 1GHz with power consumption less than 4 W.The main challenges of Godson-2G physical implementation include nanometer process technology effects,high performance design targets,and tight schedule.This paper describes the key innovative features of physical design methodology which had been used in Godson-2G physical implementation,with particular emphasis on interconnect driven floorplan generation (ICD-FP),adapted boundary constraints design optimization(ABC-OPT),automatic register group clock tree generation methodology(ARG-CTS).
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