二维离散小波提升变换算法的并行结构设计

摘要

A 2 ×2 parallel architecture for the lifting-based Two-Dimensional Discrete Wavelet Transform (2DDWT) was proposed. The architecture made use of the three inherent parallel characteristics of 2DDWT, such as row parallel, column parallel and row-column parallel to improve the execution speed and reduce the memory requirement. The proposal takes N2/4 + N/2 + 1 clocks to transform a N × N image while only 3N internal memory is required. The architecture is verified by simulation and implemented in a Stratix ⅡFPCA.%提出了一种实现二维离散小波提升变换算法(2DDWT)的2×2并行结构.该结构充分利用了2DDWT算法固有的行并行、列并行、行列并行的三种并行性,有效提高了算法执行速度,同时显著降低了硬件存储需求.处理N×N图像的时间为N2/4+ N/2+1,系统存储需求为3N.现场可编程门阵列(FPGA)实现结果证明了本设计的正确性和有效性.