A novel technique is proposed to estimate the maximum instantaneous current (MIC) in distributed sleep transistor network (DSTN) power gating circuits. Firstly, the parameters of the standard cells in the circuits are extracted and the MICs of the cells are calculated. Then the timing and placement information of the cells are processed to estimate the MICs of the clusters in the circuit. Through this proposed method the obtained MIC result is tighter and the runtime is reduced. With the estimated MICs, annealing algorithm is firstly used to do sleep transistor sizing, as well as heuristic algorithm and heuristic algorithm with A. Experimental results show that the average area overhead can be reduced to less than 1%. Finally, we verify sleep transistor sizing results by SPICE simulations and voltage drop on the virtual ground line meets well with the constraint of 5 % Vdd.%针对分布式休眠晶体管网络功率门控结构中休眠晶体管尺寸优化问题,提出一种新型的最大瞬时电流(MIC)的估算技术.首先提取电路中标准单元的相关参数,利用解析式进行单元MIC的计算,再通过处理单元的时序信息和布图信息进行电路分簇的MIC计算,可使获得的MIC约束更紧、运算速度更快；根据获得的电路MIC信息,应用启发式算法,通过引入λ因子的启发式算法和模拟退火算法分别对休眠晶体管尺寸进行了优化.优化结果显示,采用文中的技术可使休眠晶体管的面积冗余降低到1％以下,并可以缩短整个优化过程.SPICE仿真验证结果表明,将休眠晶体管插入电路后,虚拟地线上的电压降完全满足小于5％ Vdd的设计约束.
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