首页> 中文期刊> 《计算机辅助设计与图形学学报》 >基于分布式游标法的2.5D IC传输线测试

基于分布式游标法的2.5D IC传输线测试

     

摘要

为解决现有2.5DIC传输线测试方法适用性差、面积开销大和分辨率不稳定等问题提出基于分布式游标法的传输线测试方法.首先根据传输线的数量和分布情况择优选择普通游标和环形游标2种游标结构;然后把游标延时线的所有延时单元平均分配给每条传输线使所有传输线共享一条游标延时线;最后将传输线延时量化为数字码输出.实验结果表明与现有方法相比文中方法综合考虑了测试时间和面积开销满足了复杂集成电路设计的实际需要;使用2种游标结构的分布式测试方法面积开销分别减少了52.6%和23.7%;在相邻传输线间距离发生变化时测试分辨率的稳定性提高了70%.%To cope with several problems in the existing 2.5D IC interconnect test methods, such as poor applica-bility, high area overhead and resolution instability. This paper proposes a technique for interconnect testing based on distributed vernier method. First of all, two kinds of vernier structures, including regular vernier and ring ver-iner designs, were selected according to the number and distribution of the interconnect. Then, all the delay cells of the vernier delay line are evenly distributed to each interconnect, so that all interconnects share the same ver-nier delay line. Finally, the interconnect delay was quantized into digital code. In this paper, the test time and area overhead are both considered, which can meet the requirements of complex integrated circuits design. The expe-rimental results show that, the area overhead of the two distributed veriner methods are decreased by 52.6% and 23.7% respectively, compared with the existing methods. When the distance between adjacent interconnects changes, the stability of the measurement resolution is improved by 70%.

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