基于FPGA的全数字高速跳频信号发生器设计

摘要

In order to improve the frequency and clutter suppression of frequency hopping signal,a design method of full dig-ital high-speed frequency hopping frequency synthesizer based on FPGA was proposed.Based on the idea of digital control oscilla-tor ( NCO) and parallel architecture, 8-channels parallel NCO were determined. By means of low-voltage differential signaling ( LVDS) ,the full digital low-speed signal of each NCO output were serialized into high-speed signals. The results show that the sampling rate of the frequency hopping signal can reach 8 times of the single clock by using the full-digital design method,when the frequency hopping bandwidth is between 300 MHz and 550 MHz, the frequency hopping frequency clutter suppression is better than 60 dB.%为了提高跳频信号的频率,改善频率分量的杂散,提出了一种基于FP GA的全数字高速跳频频率合成器的设计方法.基于数字控制振荡器技术(NCO)和并行架构的思路确定8路并行NCO;借助低电压差分信号(LVDS)技术,将各路NCO输出的全数字低速信号串行化为高速信号.实验结果表明,采用全数字设计方法,跳频信号的采样率可达到单路时钟的8倍;跳频带宽在300～550 MHz之间时,跳频频率杂波抑制优于60 dB.