FPGA-BASED METHOD FOR DESIGNING PARALLEL PSEUDO-RANDOM SEQUENCE GENERATOR

摘要

A pseudo-random sequence generator with parallel bit width and a generator polynomial both optional, and an FPGA-based method for designing a parallel pseudo-random sequence generator. The method comprises: using a generator polynomial to obtain a one-step shift matrix, and according to the one-step shift matrix and an initial value, using MATLAB to perform a series of matrix operations to obtain an initialization logic and a feedback logic of a register bank, and setting up a hardware logic according to the initialization logic and the feedback logic. The generator has the characteristics of having arbitrary parallel number, occupying fewer logical resources, and having high clock running frequency.