基于FPGA的混沌序列发生器的设计

摘要

A new approach for the design of chaotic sequence generator is proposed:designing an IP core to produce chaotic sequences on a FPGA Embedded platform.Most of conventional methods of generating chaotic sequences are realized by software approach,which is slow and consumes a lot of resources.This paper represents a design of IP core, which can produce chaotic sequences quickly by hardware approach.On the Virtex-II Pro development platform,the IP core is added to the embedded system which is built by the EDK software,and its function is veriifed.%本文提出了一种产生混沌序列的新方法：在FPGA嵌入式系统中设计了一个用于产生混沌序列的IP核。传统的混沌序列生成方法是通过软件编程实现，序列的生成速度较慢且占用资源较多。本文设计了一个IP核，利用硬件实现混沌序列的产生，提高了序列的产生速度。本文在Virtex-II Pro开发平台上，运用EDK工具搭建了一个FPGA嵌入式平台，并添加了设计的IP核，验证了IP核的功能。