基于超混沌的伪随机数发生器的FPGA设计

摘要

The problem of the pseudo-random number generator based on hyperchaotic is that the resource occupation and the number of iterations are large.This paper designs a single precision floating-point pseudo-random number generator based on Qi hyperchaotic system.It is effective to save the system resource consumption by using the idea of time sharing and reuse and to reduce the number of system iterations by using the characteristics of high dimensional chaos and computer floating point format. The design uses Verilog HDL, modular design ideas to achieve a hyperchaotic system.Simulation results show that the generator only takes up 4 947 logic elements,the pseudo-random sequence generation rate can be up to 23.8 Mbps. Then the results in the Cyclone IV ep4ce15f17c8 development platform is given. The NIST statistical test results show that the pseudo-random sequence generated by the pseudo-random number generator can pass all 15 test items.%针对基于超混沌的伪随机数发生器占用资源高、迭代次数多等问题,设计了一种基于Qi超混沌系统的单精度浮点数伪随机数发生器.采用分时复用的思想以节省系统资源占用,并且利用高维混沌及计算机浮点数格式的特点,可以有效地减少系统迭代次数.采用Verilog HDL、模块化设计思想实现了超混沌系统的设计.仿真结果表明:本设计占用资源少,仅占4947个逻辑单元;伪随机序列生成速率最高可为23.8 Mbps;给出了在Cyclone IV ep4ce15f17c8开发平台实现结果,并且NIST统计测试结果表明该伪随机数发生器产生的伪随机序列能够通过15项测试.